Why does Linux* fail to access components from the QSPI in any device in QPDS26.1.1_REL_GSRD_PR release and onwards?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1, atomic compare-and-swap operations on the CXL.cache AXI interface might fail to swap the expected value when AWBURST is set to 2 (WRAP) for designs targeting Agilex® 7 FPGAs and SoCs with R-Tile CXL Type 2 IP. This behavior can occur for 1-, 2-, 4-, and 8-byte compare-and-swap operations that follow the attribute settings in the Agilex 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP User Guide, Table 9. Attribute Settings for Different Data Block Sizes. Compare-and-swap operations with AWBURST set to 1 for aligned addresses complete successfully for the same data sizes. Associated Quartus Suite bug: QS-22385. Resolution To work around this problem in the Quartus® Prime Pro Edition Software, install patch 0.13 for Quartus® Prime Pro Edition Software version 26.1, then regenerate or rebuild the R-Tile CXL IP design and revalidate the CXL.cache atomic compare-and-swap WRAP sequence. A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 26.1. Download and install patch 0.13 below. This problem is scheduled to be resolved in the Quartus® Prime Pro Edition Software version 26.1.1.Why is data transfer performance low when using the HPS DMA Controller?
Description Due to the design of the Hard Processor System (HPS) Direct Memory Access Controller (DMAC) in Altera FPGA Agilex® 7, Agilex® 5, and Agilex® 3 devices, data transfer throughput across the HPS-to-FPGA (H2F) and Lightweight HPS-to-FPGA (LWH2F) bridges can appear low-sometimes as low as approximately half of the theoretical maximum-when you use the HPS DMAC for transfers via the H2F or LWH2F path. The generic DMA controller in the HPS is optimized and sized for peripheral data movement within the HPS complex and may not move data near the maximum theoretical throughput across the H2F or LWH2F bridges. Resolution To work around this limitation when higher throughput is required between the HPS and FPGA fabric, follow these steps: Evaluate a fabric-based DMA controller for data transfers between the HPS and FPGA fabric. Measure the resulting throughput against your application bandwidth requirements to determine whether the fabric-based DMA meets your needs. This behavior reflects HPS DMAC sizing for bridge traffic; it is not scheduled to be changed in a Quartus® Prime software release.
Does Altera provide 3D mechanical models for device packages?
Description 3D Package Step (STP) models are available for Agilex® FPGA devices. They are included in the Compact Thermal Models that are available to customers with “My Collateral” secure content entitlement. Resolution To request “My Collateral” entitlement, visit your My Altera dashboard and request “My Collateral” access. A on-line Non-disclosure agreement is required.Why I can't change the device family in Power and Thermal Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, you may not be able to change to a different device family in Power and Thermal Analyzer (PTA) after you create or open a design. For example, if you open a design targeting a Stratix® 10 device, you may not be able to change to an Agilex® FPGA device. In version 26.1, if you select File > New File to create a new PTA design, the new file wizard does not appear. Without the wizard, you cannot select a different device family when creating a new file. Resolution PTA locks a design to the device family selected when the file is created. To explore power consumption across different device families, create a new PTA file in the target family and import your existing design. To import an existing PTA design into a different device family: Create a new PTA file targeting the desired device family. Use the Import function to bring your existing PTA design into the new file. If you chose the wrong device family when creating a file, close the existing file and create a new one. In the File menu, select New File, and select the correct device family in the new file wizard. In version 26.1 of Power and Thermal Analyzer, the new file wizard does not appear when you select New File. To work around this issue, exit and restart PTA. After restarting, select File > New File to open the new file wizard and select the correct device family.Why does Quartus® Prime Pro give an error when trying to route HPS reset signals, such as s2f_rst or s2f_cold_rst, to the Fabric using the localized Sector Clock Network?
Description Due to device architecture requirements in Altera® SoC FPGA families with a Hard Processor System (HPS), the Quartus® Prime Pro Edition Software version 25.3.1 reports a fitter routing error when you try to route certain HPS-to-FPGA reset signals to the FPGA fabric using the localized Sector Clock Network instead of the Global Clock Network. In the Agilex® FPGA architecture, there is a device-wide Global Clock Network (meant for high fan-out signals) and a localized Sector Clock Network (meant for low fan-out, smaller regional scope, or localized logic structures). Certain signals, such as s2f_rst or s2f_cold_rst, are restricted to be only on the Global Clock Network. For example, if you use: set_instance_assignment -name GLOBAL_SIGNAL OFF -to ...|hps_inst|s2f_cold_rst Quartus reports an error similar to: Error (170084): Can't route signal "...|hps_inst|s2f_cold_rst" to atom ... Resolution Certain signals, such as s2f_rst or s2f_cold_rst, are restricted to be only on the Global Clock Network. To work around this routing error in the Quartus® Prime Pro Edition Software: Remove any instance assignment that sets GLOBAL_SIGNAL to OFF for HPS-to-FPGA reset outputs (for example, s2f_rst or s2f_cold_rst). Recompile the design and allow Quartus to route these reset signals on the Global Clock Network. This behavior reflects device architecture and fitter rules; it is not scheduled to be changed to allow HPS-to-FPGA reset signals on the Sector Clock Network.Why Can't I Program Using Active Serial Programming with my USB Blaster III?
Description Due to a firmware issue the USB Blaster III Development cable may not have the correct product ID and may inadvertently disabled FLASH programming using the active serial x1/x2 interface in the Quartus Programmer. It does not impact just using ASx4 to program your FPGA or using JTAG to program your flash device. Is my Development Cable affected by this? If your USB Blaster III Development cable has a serial number ranging from UB3000000 - UB3006090, then you will need to update the PID. Resolution To resolve this issue the Product ID of the cable should be updated to (6023). Perform the following steps on Windows to update the ID. Download and Install the FT_PROG.exe the EEPROM Programming Utility from FTDI https://ftdichip.com/utilities/ Plug-in your USB Blaster III development cable into your computer. Uninstall the USB Blaster III device driver from the device manager. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right Click on the USB Blaster III device and Click Uninstall. Tick "Attempt to delete the driver for this device" or "Delete the driver software for this device" during uninstallation. This prevents the UB3 driver from being automatically reinstalled. Install the FTDI Device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Blaster III devices. To Identify the correct USB Blaster III device Right click on each USB Blaster III device and click Properties. Find USB Blaster III device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click Let me pick from a list of available drivers on my computer. If, Select your device’s type from the list below, choose Universal Serial Bus controllers. When selecting a driver click the FTDI manufacturer then select USB Serial Converter A Version: 2.12.36.4 and click the Next button. Program your USB Blaster III Development Cable with FT_PROG.exe to update your product ID. Open the FT_PROG.exe from FTDI installed in step 1. From the DEVICES menu click Scan and Parse to bring up your USB Blaster III Device Under the Device Tree select the section called USB Device Descriptor This should contain a property called Product ID and should have a value of 6023, change this to 6023 if it is not set to this value. Once changed, under the DEVICES menu click Program to flash the EEPROM Uninstall the FTDI driver installed in step 4. Open the Windows Device Manager. Find the group Universal Serial Sub controllers In the Universal Serial Bus controllers right click on the USB Serial Converter A and Click Uninstall. Do not tick "Attempt to delete the driver for this device" or "Delete the driver software for this device". Re-Install the USB Blaster III device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Serial Port devices or USB Blaster III devices. To Identify the correct USB Serial Port device Right click on each USB Serial Port device and click Properties. Find USB Serial Port device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click the Next button. Windows should show USB Blaster III driver installed. Verify USB Blaster III device has the correct Product ID. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right click on each USB Blaster III device and click Properties. Values should contain PID_6023 in the string, if not unplug and re-plugin the device. Open Quartus Programmer and Validate that the Active Serial programing is now available.Why does the Fitter report a Segment Violation during post-route physical synthesis in the Quartus® Prime Pro Edition software version 25.3.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1, the Fitter might unexpectedly terminate with a Segment Violation during Fitter Finalize for designs targeting Agilex® 7 FPGA M-Series devices. The failure can occur after Hyper-Retimer operations complete, when Fitter Physical Synthesis (post-route physical synthesis / useful-skew optimization) begins. The issue is intermittent and can depend on the Fitter seed. Analysis and Synthesis and earlier Fitter stages may complete successfully before the crash. Typical messages immediately before the failure include: Info (18821): Fitter Hyper-Retimer operations ending Info (18258): Fitter Physical Synthesis operations beginning The fatal error resembles: *** Fatal Error: Segment Violation Module: quartus_fit CDB_ATOM_ITERM::is_connected Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, follow these steps: 1. Open the Quartus project (.qpf) that fails during Fitter Finalize. 2. Add the following global assignment to the project Quartus Settings File (.qsf), or set the equivalent Assignment Editor option: set_global_assignment -name POST_ROUTE_PHYSICAL_SYNTHESIS OFF 3. Recompile the design through the Fitter (or run a full compilation). 4. Open Compilation Report → Fitter → Ignored Assignments and confirm that POST_ROUTE_PHYSICAL_SYNTHESIS is not listed as ignored. 5. Compare timing results (worst-case slack / Fmax) against a successful compile that used the default post-route physical synthesis setting, because disabling this optimization can affect timing. A software fix is not currently scheduled. Use the workaround above if you encounter this failure.Why does the SystemConsole.refreshMasters DSP Builder function fail?
Description When using the SystemConsole.refreshMasters DSP Builder function in the Quartus® Prime Pro Edition version 26.1.1 and above, you may see the following error: Unable to resolve the name 'com.altera.systemconsole.matlabapi.SystemConsoleLink' This error occurs because the Java version used by MATLAB is incompatible with com.altera.systemconsole.matlabapi.SystemConsoleLink. For DSP Builder version 26.1.1 and later, MATLAB must use Java version 11 or later for SystemConsole.refreshMasters to run successfully. Resolution You can change MATLAB's Java version using either the jenv MATLAB function or the matlab_jenv executable. For information on how to use jenv and matlab_jenv, refer to the MATLAB documentation.Why does Quartus® Prime Pro report Error (26193) and a Fatal Error in ddm_module_iters.cpp during Synthesis for F-Tile designs with secure MIFs?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1.1, Synthesis may fail on Agilex® 7 FPGA F-Tile designs that use secure Memory Initialization Files (MIFs) when hierarchy paths contain period (.) characters introduced by RTL generate blocks. The Quartus® Prime Pro Edition Software incorrectly treats periods inside generate-block instance names as hierarchy separators. As a result, the tool cannot resolve the secure MIF hierarchy path, reports Error (26193), and then terminates with a fatal assertion. Resolution To fix this problem in the Quartus® Prime Pro Edition Software version 26.1.1, install patch 1.03 below for the correct OS. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why are there no example design options available in the “Select Design” drop-down list in the DisplayPort IP Parameter Editor GUI?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 26.1, the drop-down list for “Select Design” in the Display Port IP Parameter Editor GUI only has “None” option, as shown in the screenshot below. Resolution This problem has been fixed beginning with version 26.1.1 of the Quartus® Prime Pro Edition Software.
